function in_s0; // Boot RAM
	input [31:2] a;
	begin
		in_s0 = {a[31:16], 16'b0} == 32'hffff0000;
	end
endfunction

function in_s1; // UART
	input [31:2] a;
	begin
		in_s1 = {a[31:5], 5'b0} == 32'hfffe0020;
	end
endfunction

function in_s2; // Timer
	input [31:2] a;
	begin
		in_s2 = {a[31:3], 3'b0} == 32'hfffe0008;
	end
endfunction

function in_s3; // Ethernet MAC
	input [31:2] a;
	begin
		in_s3 = {a[31:12], 12'b0} == 32'hfffe1000;
	end
endfunction

function in_s4; // Pushbuttons
	input [31:2] a;
	begin
		in_s4 = {a[31:2], 2'b0} == 32'hfffe0010;
	end
endfunction

function in_s5; // DDR3 SDRAM
	input [31:2] a;
	begin
		in_s5 = {a[31:30], 30'b0} == 32'h00000000;
	end
endfunction

function in_s6; // unused
	input [31:2] a;
	begin
		in_s6 = 1'b0;
	end
endfunction

function in_s7; // unused
	input [31:2] a;
	begin
		in_s7 = 1'b0;
	end
endfunction

// vim: ft=verilog
